1. Field of the Invention
This invention relates to the field of semiconductor devices, and more specifically, to a metal oxide semiconductor field effect transistor (MOSFET) which exhibits excellent punchthrough characteristics, and which can be realized with a VLSI manufacturable process.
2. Discussion of Related Art
In order to fabricate future complex integrated circuits, the basic building block of the integrated circuits, the transistor, must become smaller. Smaller metal oxide semiconductor transistors (MOS) are formed by decreasing the channel length of the transistor. Future MOS transistors will have channel lengths of less than 0.5 .mu.m. A problem with manufacturing such small channel devices is that the punchthrough voltage of these transistors decreases to an unacceptable level.
The punchthrough voltage of a device is the drain voltage which will cause the drain depletion region of the device to extend into the source depletion region. When this occurs the transistor conducts regardless of the gate voltage. This eliminates the ability of the transistor to act as a switch, i.e. to switch "on" and "off". MOS transistors of less than 1 .mu.m cannot be fabricated without adjusting to some degree the process recipe to raise the punchthrough voltage of the device.
Presently there are two techniques for adjusting the punchthrough voltage of short channel MOSFET transistors. The first technique, as shown in FIG. 1, employs a double-boron implant of a P type substrate to form an N channel enhancement mode MOSFET. The first boron implant, a threshold implant 12, is a shallow implant of the channel region of the device. The threshold implant raises the threshold voltage of the transistor and prevents surface punchthrough. The second boron implant, the channel implant 14, is a deeper implant of the entire channel region of the transistor. The channel implant prevents bulk punchthrough of the device.
The double-boron implant transistor is undesired because channel implant 14 adversely affects the performance characteristics of the transistor. The channel implant 14 is especially troublesome because it raises the doping at the depletion edge of the device, which affects the device's substrate sensitivity. Additionally, the channel implant adversely affects the sub-threshold slope (gate swing voltage) of the device and also affects threshold voltage.
The second punchthrough voltage adjusting technique is known as LATIPS, and is shown in FIG. 2. The LATIPS transistor employs a large tilt-angle implanted punchthrough stopper (LATIPS). This implant forms higher concentration P type regions 16 under the gate to prevent bulk punchthrough. This implant is generated by tilting and rotating the wafer as the implant occurs. The LATIPS transistor also employs a threshold implant 18 to raise the threshold voltage and to prevent surface punchthrough.
The LATIPS transistor exhibits several undesirable features. First, the P implants 16 do not surround the entire drain. This requires wells to be deeper to prevent well punchthrough, leading to a reduction in packing densities. Second, the LATIPS technology has not been characterized extensively, making its successful use in the manufacturing environment questionable. This is because the rotational aspect of the punchthrough implant provides a doping uniformity which is dependant on the placement, shape, and layout of the fabricated transistor. Additionally, the LATIPS technique requires very specialized and expensive equipment which is difficult to obtain.
Thus, what is needed is a submicron transistor which exhibits excellent punchthrough characteristics without sacrificing other device performance characteristics and which can be fabricated with a VLSI manufacturable process.